Voltage regulation circuits have many applications in power supply systems to provide a regulated voltage at a predetermined multiple of a reference voltage. In low drop-out regulator designs, power supply drop-out can be an issue due to higher frequency switching, load dump and higher power consumption. Two of the issues that can arise from high frequency operations are start-up settling time specification and steady state supply load dump recovery specification. There is consequently room for improvement in the design of low drop out regulation circuits.
In LDO design, using Miller capacitance compensation techniques in feedback control loop can be an effective approach to achieve stability while using less silicon area for a design. One of the drawbacks of using Miller capacitance compensation is the existence of two closed feedback loops for the Op-amp. Normally, under a small signal model there is only one closed feedback loop, namely that from the op-amp's output through the feedback network, and then through the error amplifier to the final output. This known engineering effect is used to improve the circuit's bandwidth and stability. However, if output of the op-amp is significantly disturbed, such as is the case when connecting to a load or when the load has fast switching characteristics, then a second closed loop formed from the output through the miller capacitance directly to the output of error amplifier and then on to the output of the op-amp. This second closes loop will dominate over the normal closed loop due to its high frequency nature as the Miller capacitance is acting as short circuit at high frequencies. The combined result of the fast closes loop plus original closes loop is a longer settling time due to the slew rate of error amplifier, basically, a dominant pole exists under this transition at output of error amplifier. In LDO designs using dominant pole compensation at the output of LDO, this will improve Power Supply Rejection Ratio (PSRR) over the entire frequency range, but will use large amounts of power and relatively large silicon area for physical capacitance. This type of compensation scheme limits the circuit's dynamic performance due to its slew rate in initial settling time and steady state load dump recovery speed.